Multilayer ceramic chip capacitors have been widely utilized as miniature size, high capacitance, high reliability electronic parts. In accordance with increasing demands for smaller, high-performance electronic equipment, multilayer ceramic chip capacitors also have encountered more rigorous demand toward smaller size, higher capacitance, lower cost, and higher reliability.
Multilayer ceramic chip capacitors generally are fabricated by forming alternating layers of an internal electrode-forming paste and a dielectric layer-formiing paste. Such layers may be formed by sheeting, printing, and similar techniques followed by concurrent firing.
Generally, the internal electrodes have been formed of conductors such as Pd and Pd alloys. Although palladium is expensive, it can be partially replaced by the use of relatively inexpensive base metals such as Ni and Ni alloys. The term "base metal" is defined as any metal other than a metal of the precious metal groups (gold, silver, and platinum). Since internal electrodes of base metals become oxidized if fired in ambient air, the dielectric layers and internal electrode layers must be co-fired in a reducing atmosphere. Firing in a reducing atmosphere, however, causes the dielectric layers to be reduced, resulting in a lowering of resistivity. Multilayer ceramic chip capacitors using non-reducible dielectric materials have been proposed; however, such devices typically have a shorter life of insulation resistance (IR) and low reliability.
When the dielectric material is subject to a DC electric field, its relative dielectric constant (K) lowers with time. If thinner dielectric layers are used in order to provide chip capacitors of a smaller size and greater capacitance, application of DC voltages across the capacitor causes the dielectric layers to receive a more intense electric field, resulting in a greater change of dielectric constant (K) with time, that is, a greater change of capacitance with time. Such changes are undesirable in most applications.
Capacitors also are required to have good DC bias performance. The term "DC bias performance," also referred to as the voltage coefficient of capacitance (VCC), is defined as the rate of change of capacitance with a change in DC bias (voltage). The capacitance generally decreases as the applied DC electric field is increased. Capacitors having poor DC bias performance thus have the problem that when a DC electric field is applied across the capacitors during normal operation, capacitance drops to unacceptable levels.
The Electronic Industry Association (EIA) prescribes a standard for temperature coefficient of capacitance (TCC) known as the X7R characteristic. The X7R characteristic requires that the rate of change of capacitance be within .+-.15% (reference temperature 25.degree. C.) over the temperature range -55.degree. C. to 125.degree. C.
U.S. Pat. No. 5,335,139 to Nomura discusses various prior efforts. According to Nomura, one dielectric material known to meet the X7R characteristic is a composition of the BaTiO.sub.3 +SrTiO.sub.3 +MnO system described in Japanese Patent Application Kokai (JP-A) No. 36170/1986. This material, however, is said to experience a great change of capacitance with time under a DC electric field, for example, a capacitance change of -10% to -30% when a DC electric field of 50 volts is applied at 40.degree. C. for 1,000 hours. This change fails to meet the X7R characteristic.
Other non-reducible dielectric porcelain compositions discussed by Nomura include the BaTiO3+MnO+MgO system described in JP-A 71866/1982; the (Ba.sub.1-x Sr.sub.x O).sub.a Ti.sub.1-y Zr.sub.y O.sub.2 +.alpha.((1-x)MnO+zCoO)+.beta.((1-t)A.sub.2 O.sub.5 +tL.sub.2 O.sub.3 +wSiO.sub.2 system disclosed in JP-A 250905/1986, wherein A is Nb, Ta, or V, and L is Y or a rare earth element; and barium titanate having added thereto Ba.sub.a Ca.sub.1-a SiO.sub.3 in vitreous state as disclosed in JP-A 83256/1990. It is said that these dielectric porcelain compositions could not meet all the requirements including good temperature dependence of capacitance, a minimized change of capacitance with time under a DC electric field, good DC bias performance, and a long accelerated life of insulation resistance. For example, the compositions of JP-A 250905/1986 and 83256/1990 are said to have a short accelerated life of insulation resistance.
Nomura, U.S. Pat. No. 5,335,139, describes a multilayer ceramic chip capacitor having alternately stacked dielectric layers and internal electrode layers which may be formed of nickel or nickel alloy. In one embodiment, the dielectric layers contain barium titanate as a major component and magnesium oxide, manganese oxide, barium oxide and/or calcium oxide, silicon dioxide, and yttrium oxide as minor components in such proportion that there are present 0.1 to 3 mol of MgO, 0.05 to 1.0 mol of MnO, 2 to 12 mol of BaO+CaO, 2 to 12 mol of SiO.sub.2 and up to 1 mol of Y.sub.2 O.sub.3 per 100 mol of BaTiO.sub.3. Nomura teaches that samples containing less than 0.1 mol magnesium oxide per 100 mol of BaTiO.sub.3 fail to provide the desired temperature dependence of capacitance.
It is desirable to have yttrium oxide present in the ceramic composition to ensure high reliability, provide high resistance to dielectric breakdown, and prevent degradation. However, when yttrium oxide and magnesium oxide are both present in the composition, they tend to interact in a manner which causes the rate of change of capacitance to fall outside of the X7R characteristic at the high end of the temperature range, i.e., 125.degree. C. It would thus be desirable to develop a composition which contains yttrium oxide but no magnesium oxide in order to form capacitors having high reliability and high resistance to DC voltage breakdown while meeting the X7R characteristic at 125.degree. C.